1. Field of the Invention
The present invention relates to a method of manufacturing capacitor in semiconductor devices, and more particularly, to a method of manufacturing a capacitor in a semiconductor devices capable of preventing decrease in the reliability and yield of the devices due to etch damage of a lower copper electrode, by forming a MIM (metal-insulator-metal) capacitor using copper as the lower electrode by means of chemical mechanical polishing process without using mask process and etch process.
2. Background of the Related Art
Generally, as the semiconductor industry shifts to an ultra large-scale integration (ULSI), the geometry of the device is continuously narrowed to a sub-half-micron region while the circuit density such as improved performance and reliability is also increased. In suit with this request, in forming metal lines of the semiconductor devices, a copper thin film has been used as an interconnection material useful for the integration circuit. The reason why the copper thin film is used as the interconnection material is that it can improve reliability of the semiconductor devices since the copper thin film has a higher melting point than aluminum and has high resistance to electro-migration (EM), and increase the signal transfer speed since it has a low resistivity. Further, the damascene scheme, by which a via contact hole for electrically connecting the lower layer and the trench where the metal line is located are formed at the same time, has been widely applied to the process of forming the copper line in the semiconductor devices. A metal interlayer insulating film in which the damascene pattern will be formed is formed of a low dielectric insulating material having a low dielectric constant.
Meanwhile, in the MIM (metal-insulator-metal) capacitor of the semiconductor device using the copper line, copper is used as the lower electrode and materials such as Ti, TiN, Ta, TaN, and the like are used as the lower electrode. A conventional method of manufacturing the MIM capacitor includes sequentially performing the processes of forming the lower copper electrode by means of the damascene scheme, depositing a capacitor dielectric film on the entire structure including the lower copper electrode, an upper electrode material layer on the capacitor dielectric film, forming and upper electrode mask layer on the upper electrode material layer by means of photolithography process and etching the upper electrode material layer and the capacitor dielectric film by means of etch process using the mask layer, thus forming the upper electrode.
However, in the above conventional process, the process of etching the upper electrode material layer and the capacitor dielectric film is used. During the etch process, there occurs a difficulty in controlling the processes since etch damage of the lower copper electrode occurs and copper polymer that is difficult to remove is generated. Further, damage of the lower electrode and generation of copper polymer ultimately adversely affects the yield of the devices.